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Intel SoC Design Engineer in Phoenix, Arizona

Job Description

As a SoC Design Engineer, you'll be responsible for but not limited to the following:

  • Develop and test Engineering Design Automation tools, creates flows/scripts to analyze and test design methodologies.

  • Responsible for designing, deploying and testing efficiency of tools to utilize in achieving design goals and collaborating with design teams on methodology development.

  • Develop/Test/Support RF PDK Development activities.

  • Work with Industry standard EDA software such as Cadence, Mentor, Synopsys & EM tools.

  • Responsible for EM/RV/QA/Fill/APR/Extraction flows, support, collateral creation, PDK and kit integration.

  • Creation and execution of QA test cases and regression suites.

  • Apply design methodologies to help execute projects effectively and successfully with high quality.


Minimum requirements:

  • Selected candidate must possess a BS in EE/CE/CS with 4+ years of relevant experience or MS in EE/CE/CS with 3+ of relevant experience in IC Design, ASIC or Computer Aided Design CAD.

  • Demonstrate experience in CMOS Design (front-to-back), ASIC Design and RF/Analog flows, collateral PDK.

  • Understanding of CMOS (finfet) Integrated Circuit IC, Layout, Verification, ASIC flows and related methodologies.

  • Working with Cadence, Synopsys and Mentor tools is expected along with the ability to define and develop PDK, with experience in RF/Analog/Digital/EM flows.

Preferred requirements:

  • Experience with Skill programming and developing GUI interfaces is preferred.

  • Programming skills: Unix Shell, Perl, Python, Skill, Tcl, Pcell coding.

  • Experience with Mentor Calibre, SmartFill and/or Synopsys ICV, development and support of robust and efficient Design Rule Check (DRC) and Layout Versus Schematic (LVS) runsets

  • Demonstrate experience with Cadence DFII environment such as Schematic Composer & Virtuoso Layout Editor.

  • Fast-Spice Simulators such as Spectre etc. Mentor Graphics software such as Calibre for DRC/LVS/PEX and/or Star-RCXT for Parasitic Extraction, Cadence QRC for extraction

  • Demonstrate expertise with EDA software & flows

  • 3+ years' with industry based (CAD) layout tools include: Cadence Virtuoso, Calibre, DRC/LVS runset and algorithm development.

Important behavior traits:

  • Communication and presentation skills

  • Team player and self-motivated technical individual aligned with Intel values


Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth

Other Locations

US, California, Santa Clara;US, Oregon, Hillsboro

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.